AMD Am79C930 Manual do Utilizador

PRELIMINARYThis document contains information on a product under development at Advanced Micro Devices. Theinformation is intended to help you evalua

AMDP R E L I M I N A R Y10Am79C930TIR10: TX FIFO Data Register 95. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AMDP R E L I M I N A R Y100Am79C930TIR21: CRC32 Correct Byte Count MSBThis register is the CRC32 Correct Byte CountMSB register.Bit Name Reset Value

P R E L I M I N A R YAMD101Am79C930TIR24: TCR Index RegisterThis register is the TCR Index register. This register isused as an address into indire

AMDP R E L I M I N A R Y102Am79C9302 ADDA 0 A/D D/A mode. ADDA is used with ENEXT (TCR25[6]), ENSAR(TCR25[5]), and UXA2DST (TCR25[7]) to determine t

P R E L I M I N A R YAMD103Am79C930TIR28: RSSI Lower LimitThis register is the RSSI Lower Limit register. The valuein this register is compared agai

AMDP R E L I M I N A R Y104Am79C930TIR31: TESTThe TAI TEST register is a reserved location.Bit Name Reset Value Description 7 Reserved 0 These bit

P R E L I M I N A R YAMD105Am79C930ProgrammedSD[1:0] Start of Frame Detect Operation Register00 Start of Frame Detect Off None01 Search for 8 bit St

AMDP R E L I M I N A R Y106Am79C930TCR2: Clock RecoveryThis register is the Clock RecoveryConfiguration register.Bit Name Reset Value Description C

P R E L I M I N A R YAMD107Am79C930to delay the start of CRC8 and CRC32 and DC bias controlcalculation for both receive and transmit frames. The p

AMDP R E L I M I N A R Y108Am79C930TCR6: TX Ramp Down TimingThis register is the TX Ramp Down Timing register.This register determines the ramp do

P R E L I M I N A R YAMD109Am79C930In addition, the USER5/IRQ4 pin may be used to produce interruptsto the 80188 embedded controller. This capabili

P R E L I M I N A R YAMD11Am79C930TCR24: RSSI Sample Start 117. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AMDP R E L I M I N A R Y110Am79C930has also been set to a 1 and the PCMCIA pin is set to 1. The valuethat is read from this bit represents the curr

P R E L I M I N A R YAMD111Am79C930Delimiter may be used for start of frame recognition by appropriatesettings of the SD[1:0] bits in the Network Co

AMDP R E L I M I N A R Y112Am79C930TCR13: Pin Configuration AThis register is the Pin Configuration A register. Thisregister is used to set the sta

P R E L I M I N A R YAMD113Am79C930value that is present on the LLOCKE pin, regardless of the setting ofthe PCMCIA pin.The control of the function

AMDP R E L I M I N A R Y114Am79C930In addition to these bits, the USER6/IRQ5 pin may be used to pro-duce interrupts to the 80188 embedded controll

P R E L I M I N A R YAMD115Am79C930TCR17: Baud Detect Lower LimitThis register is the Baud Detect Lower Limitregister (TCR17). CONFIGURATION RE

AMDP R E L I M I N A R Y116Am79C930edge baud counter. This information should be used to appropri-ately program the Baud Detect Upper Limit register

P R E L I M I N A R YAMD117Am79C930CONFIGURATION REGISTER INDEX: 15hBit Name Reset Value Description 3–0 BDRN[3:0] 0h Baud Detect Ratio. These bits

AMDP R E L I M I N A R Y118Am79C930CONFIGURATION REGISTER INDEX: 18hBit Name Reset Value Description 7:6 Reserved – Reserved. Must be written as a

P R E L I M I N A R YAMD119Am79C9303–0 A2DT[3:0] 1010b A/D sampling Time[3:0]. The value in the A2DT[3:0] field deter-mines the duration of time r

AMDP R E L I M I N A R Y12Am79C930TIMING WAVEFORMS 148. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AMDP R E L I M I N A R Y120Am79C930TCR26: ReservedThis register is the TAI reserved location register.CONFIGURATION REGISTER INDEX: 1AhBit Name Res

P R E L I M I N A R YAMD121Am79C930be high assert, such that when the TGAP2 counter expires, theTXMOD pin will be driven to a HIGH logic level.TCR2

AMDP R E L I M I N A R Y122Am79C930is set to a 0, the Baud Detect Count for Stop Diversity is not used inthe stop diversity decision logic.1 UBDCS

P R E L I M I N A R YAMD123Am79C930then a 16-bit deep serial FIFO is inserted into the TX data path. ThisFIFO allows for some mismatch to be toler

AMDP R E L I M I N A R Y124Am79C930PCMCIA CCR Registers and PCMCIACIS SpaceTwo bytes of attribute memory space have beenused by the Am79C930 device

P R E L I M I N A R YAMD125Am79C930When written with a 1, the PWRDWN bit generates an interrupt tothe 80188, requesting that the 80188 core place th

AMDP R E L I M I N A R Y126Am79C930ABSOLUTE MAXIMUM RATINGSStorage Temperature: –65 to +150°C. . . . . . . . . . . . Ambient Temperature Under Bi

P R E L I M I N A R YAMD127Am79C930DC CHARACTERISTICS (continued)5.0 V Am79C930 DC CharacteristicsParameterSymbol Parameter Description Test Co

AMDP R E L I M I N A R Y128Am79C930ABSOLUTE MAXIMUM RATINGSStorage Temperature: –65 to +150°C. . . . . . . . . . . . Ambient Temperature Under Bi

P R E L I M I N A R YAMD129Am79C930DC CHARACTERISTICS (continued)3.3 V Am79C930 DC CharacteristicsParameterSymbol Parameter Description Test Co

Am79C930 13 PRELIMINARY PCMCIA CONNECTION DIAGRAM Notes: Pin 1 is marked for orientation.NC = No Connection636465666768697071727374757677787980818283

AMDP R E L I M I N A R Y130Am79C930ABSOLUTE MAXIMUM RATINGSStorage Temperature: –65 to +150°C. . . . . . . . . . . . Ambient Temperature Under Bi

P R E L I M I N A R YAMD131Am79C930AC CHARACTERISTICS5.0 AND 3.3 V PCMCIA INTERFACEABSOLUTE MAXIMUM RATINGSStorage Temperature: –65 to +150*C. .

AMDP R E L I M I N A R Y132Am79C930PCMCIA MEMORY WRITE ACCESSParameterSymbol Parameter Description Test Conditions Min Max UnittAVWL Address setu

P R E L I M I N A R YAMD133Am79C930PCMCIA I/O READ ACCESSParameterSymbol Parameter Description Test Conditions Min Max UnittAVIGL Address setup t

AMDP R E L I M I N A R Y134Am79C930PCMCIA I/O WRITE ACCESSParameterSymbol Parameter Description Test Conditions Min Max UnittAVIWL Address setup

P R E L I M I N A R YAMD135Am79C930AC CHARACTERISTICS5.0 AND 3.3 V ISA INTERFACE ABSOLUTE MAXIMUM RATINGSStorage Temperature: –65 to +150°C. . .

AMDP R E L I M I N A R Y136Am79C930ISA ACCESSParameterSymbol Parameter Description Test Conditions Min Max Unitti1 LA[23:17] valid setup to BALE

P R E L I M I N A R YAMD137Am79C930AC CHARACTERISTICS5.0 V MEMORY BUS INTERFACEABSOLUTE MAXIMUM RATINGSStorage Temperature: –65 to +150°C. . . .

AMDP R E L I M I N A R Y138Am79C930MEMORY BUS WRITE ACCESSParameterSymbol Parameter Description Test Conditions Min Max UnittmAD MA[16:0] valid f

P R E L I M I N A R YAMD139Am79C930AC CHARACTERISTICS3.3 V MEMORY BUS INTERFACEABSOLUTE MAXIMUM RATINGSStorage Temperature: –65 to +150°C. . . .

14 Am79C930 PRELIMINARY PCMCIA PIN SUMMARYListed by Pin Number Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name 1 USER2 37 MA10 73

AMDP R E L I M I N A R Y140Am79C930MEMORY BUS WRITE ACCESSParameterSymbol Parameter Description Test Conditions Min Max UnittmAD MA[16:0] valid f

P R E L I M I N A R YAMD141Am79C930AC CHARACTERISTICS5.0 V TAI INTERFACE ABSOLUTE MAXIMUM RATINGSStorage Temperature: –65 to +150°C. . . . . . .

AMDP R E L I M I N A R Y142Am79C9305.0 V TAI INTERFACE AC CHARACTERISTICSParameterSymbol Parameter Description Test Conditions Min Max UnitTCLKIN

P R E L I M I N A R YAMD143Am79C930Notes:1. Only applicable when TXC has been configured as an INPUT.2. Only applicable when TXC has been configure

AMDP R E L I M I N A R Y144Am79C930AC CHARACTERISTICS3.3 V TAI INTERFACEABSOLUTE MAXIMUM RATINGSStorage Temperature: –65 to +150°C. . . . . . . .

P R E L I M I N A R YAMD145Am79C9303.3 V TAI INTERFACE AC CHARACTERISTICSParameterSymbol Parameter Description Test Conditions Min Max UnittCLKIN

AMDP R E L I M I N A R Y146Am79C930AC CHARACTERISTICS5.0 AND 3.3 V USERPROGRAMMABLE PINS ABSOLUTE MAXIMUM RATINGSStorage Temperature: –65 to +150

P R E L I M I N A R YAMD147Am79C930AC CHARACTERISTICS5.0 AND 3.3 V IEEE 1149.1 INTERFACE ABSOLUTE MAXIMUM RATINGSStorage Temperature: –65 to +150

AMDP R E L I M I N A R Y148Am79C930TIMING WAVEFORMSPCMCIA Bus Interface WaveformsAn, REGCEOEDo (Dout)tAVQVtELQVtGLQVtGLQNZtGHAXtGHQZWE(high)WAIT

P R E L I M I N A R YAMD149Am79C93020138B-12AnREGIORDDo (Dout)WAITtAVIGLCEtIGHRGHtRGLIGLtIGHAXtELIGLtIGLIGHtIGLWTLtWTLWTHtIGHEHtWTHQVtIGHQXtIGLQV

Am79C930 15 PRELIMINARY PCMCIA PIN LISTListed by Pin Name Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. A0 46 HFPE 120 OE 70 TX

AMDP R E L I M I N A R Y150Am79C930ISA Bus Interface Waveforms20138B-14**CMD = one of: MEMR, MEMW, IOR, IOWLAnCMD**SDout (read)ti1ti8ti34ti3ti14I

P R E L I M I N A R YAMD151Am79C930Memory Bus Interface Waveforms20138B-15MAnFCE, SCE, XCEMOEMDi (Din)tmAAtmOEtmADMWE(high)CLKINtmRDSCtmACStmHdata

AMDP R E L I M I N A R Y152Am79C930CLOCK WAVEFORMS20138B-17CLKIN0.8 V2.0 VtCLINtINHLtCLKINtINLHtCHIN0.8 VTXC0.8 V2.0 VtCLTXtTXHLtTXCtTXLHtCHTX0.8 V

P R E L I M I N A R YAMD153Am79C930TAI WAVEFORMS20138B-18**ICO = Internally Controlled OutputICO*RCO**RCO**tn1CLKINCLKOUT (internal)tn2RCO**tn3tn4

AMDP R E L I M I N A R Y154Am79C930 PROGRAMMABLE INTERFACE WAVEFORMS20138B-20**RCO = Register Controlled OutputWAIT or IOCHRDYRCO**(data change)C

P R E L I M I N A R YAMD155Am79C930IEEE 1149.1 INTERFACE WAVEFORMS20138B-21TCKTDI, TMSTDOt31Output Signalst25t30t32t34t37t36Input Signalst35Figure

AMDP R E L I M I N A R Y156Am79C930AC TEST REFERENCE WAVEFORMS5.0 V PCMCIA AC Test Reference WaveformThis waveform indicates the AC testing method

P R E L I M I N A R YAMD157Am79C9305.0 V NON-PCMCIA AC TEST REFERENCE WAVEFORMThis waveform indicates the AC testing method em-ployed for all signa

AMDP R E L I M I N A R Y158Am79C930PHYSICAL DIMENSIONSPQT144144-Pin Thin Quad Flat Pack (measured in millimeters)1.00 REF.1.60 MAX11° – 13°11° –

A-1Am79C930Typical Am79C930 System ApplicationAPPENDIX AHostComputer128KFlash128KSRAMAm79C930Radioor IRTransceiverPCMCIAor ISA PnPInterfa

16 Am79C930 PRELIMINARY PCMCIA PIN FUNCTION SUMMARYPCMCIA Pin Summary No. of Pins Pin Name Pin Function Pin Style 15 A14–A0 PCMCIA address bus lines

AMDA-2 Am79C9301. Command and status communication2. Data buffer areas3. Am79C930 80188 core variable spaceAfter performing these functions, the dev

Trademarks Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved.AMD, the AMD logo, and combinations thereof are trademarks of Advanced M

Am79C930 17 PRELIMINARY PCMCIA PIN FUNCTION SUMMARY (continued)PCMCIA Pin Summary (continued) No. of Pins Pin Name Pin Function Pin Style 1 TDO Test

18 Am79C930 PRELIMINARY PCMCIA PIN FUNCTION SUMMARY (continued)PCMCIA Pin Summary (continued)Output Driver TypesInput Types No. of Pins Pin Name Pin

Am79C930 19 PRELIMINARY ISA PLUG AND PLAY BLOCK DIAGRAMJTAGControlBlockTRSTTMS/T3TDI/T1TDO/T2RXCINANTSLTANTSLTSAR6–0ADIN2–1ADREFRXDATASDCLKSDDATASDSE

2 Am79C930 PRELIMINARY ORDERING INFORMATIONStandard Products AMD standard products are available in several packages and operating ranges. The order

20 Am79C930 PRELIMINARY ISA PLUG AND PLAY CONNECTION DIAGRAM Notes: Pin 1 is marked for orientation.NC = No Connection6364656667686970717273747576777

Am79C930 21 PRELIMINARY ISA PLUG AND PLAY PIN LISTListed by Pin Number Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name 1 LA19 37

22 Am79C930 PRELIMINARY ISA PLUG AND PLAY PIN LIST Listed by Pin Name Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. ACT 98 MA11

Am79C930 23 PRELIMINARY ISA PLUG AND PLAY PIN SUMMARY No. of Pins Pin Name Pin Function Pin Style 7 LA23–LA17 ISA upper address bus lines I17 SA16–SA

24 Am79C930 PRELIMINARY ISA PLUG AND PLAY PIN SUMMARY (continued)Output Driver TypesInput Types No. of Pins Pin Name Pin Function Pin Style 1 TXC Tra

P R E L I M I N A R YAMD25Am79C930PIN DESCRIPTIONSPins with Internal Pull Up or PullDown DevicesSeveral pins of the Am79C930 device include intern

AMDP R E L I M I N A R Y26Am79C930The functionality of the following pins is determined, atleast in part, by the connection of the PCMCIA pin:PCMC

P R E L I M I N A R YAMD27Am79C930Function Mode REG CE1 IORD IOWR A0 OE WE D7–0Standby mode X H X X X X X High-ZCommon Memory Read Even Byte H L H

AMDP R E L I M I N A R Y28Am79C930IORI/O ReadInputThe IOR signal is made active by the ISA host in order toread data from the Am79C930 device’s I/O

P R E L I M I N A R YAMD29Am79C930Clock PinsCLKINSystem ClockInputCLKIN is the clock input for the Am79C930 device’slogic functions. CLKIN is used

Am79C930 3 PRELIMINARY BLOCK DIAGRAMPCMCIA ModeJTAGControlBlockTRSTTMS/T3TDI/T1TDO/T2RXCINANTSLTANTSLTSAR6–0ADIN2–1ADREFRXDATASDCLKSDDATASDSEL3–1TXCM

AMDP R E L I M I N A R Y30Am79C930is deasserted when the RESET pin is issued or the CRCreset bit is set to 1 (SIR0); when the TXS bit is set to 1(T

P R E L I M I N A R YAMD31Am79C930TXMODTransmit Modulation EnableOutputTXMOD is an active low output that is used to enable thetransmit modulation

AMDP R E L I M I N A R Y32Am79C930IEEE 1149.1 Test Access Port PinsTCKTest ClockInputTCK is the clock input for the boundary scan test modeoperatio

P R E L I M I N A R YAMD33Am79C930VDDT, VDDU1,VDDU2, VDDP, AcceptableVCC VDDM AVDD, VDD5 Combination5 V All at 5 V Both at 5 V Yes3 V All at 5 V Bot

AMDP R E L I M I N A R Y34Am79C930for an output function. This means that there are con-figurations for which a read of the pin data register bit w

P R E L I M I N A R YAMD35Am79C930Note that a read of the USERDT[0] bit (TIR29[0]) will al-ways give the current USER0/RFRSH pin value, regard-less

AMDP R E L I M I N A R Y36Am79C930Pin 94: RXC/IRQ10/EXTA2DSTThe RXC/IRQ10 pin may be configured for input opera-tion, output operation, ISA IRQ10 o

P R E L I M I N A R YAMD37Am79C930ENXCHBSY bit of TCR28 and the CHBSYU bit ofTIR5 and operates independently of the bits in thetable below.In addi

AMDP R E L I M I N A R Y38Am79C930Pin 101: SDCLKThe SDCLK pin may be configured for input or outputoperation. The output drive may be programmed fo

P R E L I M I N A R YAMD39Am79C930Pin 115: TXCThe TXC pin may be configured for input or output op-eration according to the table below:TXC input

4 Am79C930 PRELIMINARY BLOCK DIAGRAMBus Interface UnitA14–0 or LA23–17, SA16–0D7–0CLKINSlave Control PCMCIA and ISA Memory and I/OAddress BufferData

AMDP R E L I M I N A R Y40Am79C930Pin 126: TXCMDThe TXCMD pin may be configured to drive a trans-ceiver control reference signal, using one of two

P R E L I M I N A R YAMD41Am79C930some functionality is only available in PCMCIA mode.Pin functionality is programmed according to the follow-ing t

AMDP R E L I M I N A R Y42Am79C930LLOCKE/ LLOCKE/PCMCIA LLOCKEN SA15 Pin SA15 PinPin Value TCR14[6] Direction Value0 X I NA (SA15 input function)10I

P R E L I M I N A R YAMD43Am79C930PCMCIA Interface — The Am79C930 device fully sup-ports the PCMCIA standard, revision 2.1.The PCMCIA interface on

AMDP R E L I M I N A R Y44Am79C930ISA (IEEE P996) Plug and Play Interface — TheAm79C930 device fully supports the ISA Plug and Playspecification, r

P R E L I M I N A R YAMD45Am79C930Memory InterfaceThe memory interface is provided to support direct con-nection of both a non-volatile memory (typ

AMDP R E L I M I N A R Y46Am79C930the media is considered busy and the MAC should deferto the existing message. This function is implemented inhard

P R E L I M I N A R YAMD47Am79C930accesses to use the memory interface bus during the T1and T2 cycles of the 80188 access. The Memory Ad-dress Bus

AMDP R E L I M I N A R Y48Am79C930Transceiver Attachment Interface UnitThe TAI Unit includes the following subfunctions:TAI register setTX FIFOTX d

P R E L I M I N A R YAMD49Am79C930T1TXDATAT2T32 X TSCLKTGAP2 X TBCLK + 2 X TSCLKTGAP1 X TBCLK + 2 X TSCLK1st Data BitLast Data Bit2 X TSCLKTXS4

Am79C930 5 PRELIMINARY BLOCK DIAGRAMTransceiver Attachment Interface UnitC R CMA[4:0]MD[7:0]CLKINSlave Control Memory Interface Bus I/O and DMATIR0

AMDP R E L I M I N A R Y50Am79C930Transceiver-Based TX Power Ramp Control — TheCTS signal may be used to synchronize operations be-tween the Am79C9

P R E L I M I N A R YAMD51Am79C930values were found to be correct. These register valuescan be used to determine the end of a received frame.When go

AMDP R E L I M I N A R Y52Am79C930register of TCR4. ADIN2 becomes active after ADIN1 bythe amount of delay specified in the RSSI Sample Starttime of

P R E L I M I N A R YAMD53Am79C930resolution is equal to twice the CLKIN period when theCLKGT20 bit of MIR9 is set to 1. (For a 1 MB data ratewith

AMDP R E L I M I N A R Y54Am79C930CCA ResultUBDCS URSSI Baud Detect Carrier RSSI >= RSSI (CHBSY BitTCR28:1 TCR28:0 Sense Decision Lower Limit o

P R E L I M I N A R YAMD55Am79C930Diversity decision logic for determining if a satisfactoryantenna has been found. These inputs to the Stop Di-ver

AMDP R E L I M I N A R Y56Am79C930The following is a brief summary of the IEEE 1149.1compatible test functions implemented in theAm79C930 device:Bo

P R E L I M I N A R YAMD57Am79C930mode, the host requests a power down by writing to thePower Down bit (bit 2) of the PCMCIA Card Configura-tion and

AMDP R E L I M I N A R Y58Am79C930Writing a 1 to the Power Down bit of the ISA PowerDown bit of SIR3 will cause a request for a power downto be gene

P R E L I M I N A R YAMD59Am79C930Am79C930 Device PCMCIA Mode Resource RequirementsCommon Common Attribute AttributeMemory Range Memory Size I/O Ra

AMDP R E L I M I N A R Y6Am79C930TABLE OF CONTENTSDISTINCTIVE CHARACTERISTICS 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AMDP R E L I M I N A R Y60Am79C930Some of the Am79C930 device’s PCMCIA CommonMemory locations have predefined uses and, therefore,are not freely ava

P R E L I M I N A R YAMD61Am79C930The SRAM is intended to serve as a shared memory re-source between the driver operating through the systeminterfa

AMDP R E L I M I N A R Y62Am79C930Am79C930 Device PCMCIA Mode Attribute Memory Restricted Space PCMCIA Addressin Attribute Memory SIR1[5:3] Siz

P R E L I M I N A R YAMD63Am79C930The following table indicates the mapping of all I/O re-sources that are accessible through the Am79C930PCMCIA sys

AMDP R E L I M I N A R Y64Am79C930Am79C930 Device ISA Plug And Play Mode Memory And I/O Resource Requirements Memory Range Memory Size I/O Range I/

P R E L I M I N A R YAMD65Am79C930address needs to be aligned to a 32K boundary in mem-ory space. This alignment requirement should be in-cluded in

AMDP R E L I M I N A R Y66Am79C930The SRAM is intended to serve as a shared memory re-source between the driver operating through the systeminterfac

P R E L I M I N A R YAMD67Am79C930Am79C930 Device ISA Plug And Play Mode I/O MAP PhysicalISA SIR1 Resource Location ofResource Name Mnemonic I

AMDP R E L I M I N A R Y68Am79C930ISA Plug and Play Register Set — The Am79C930 de-vice fully supports the ISA Plug and Play specification,revision

P R E L I M I N A R YAMD69Am79C930Am79C930 Device ISA Plug And Play Mode Plug And Play Register Set ISA Plug and Play Plug and Play PortRegister

P R E L I M I N A R YAMD7Am79C930Pin 3: USER4/LA17 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AMDP R E L I M I N A R Y70Am79C930The Am79C930 device maps the Resource Data regis-ter accesses into 1K–16 of the upper 1 Kbytes of theFlash memory

P R E L I M I N A R YAMD71Am79C93080188 Core Memory Map Using Scheme “A”, LMCS=1FF8h, UMCS=E038h, MIR0[6]=0 Active80188 Address Active 80188 A

AMDP R E L I M I N A R Y72Am79C930MAC (80188 core) Memory ResourcesRestrictions — Some of the Am79C930 device 80188core’s memory locations have pre

P R E L I M I N A R YAMD73Am79C930to TIR10. It is also possible to use 80188 MOV instruc-tions to unload RX data from the RX FIFO. The RX FIFOmay be

AMDP R E L I M I N A R Y74Am79C930The sleep state machine is returned to its idle state(i.e., awake).The memory bus arbitration state machine is re-

P R E L I M I N A R YAMD75Am79C930The sleep state machine is returned to its idle state(i.e., awake).The following registers and state machines areU

AMDP R E L I M I N A R Y76Am79C930The MIR space contains 16 registers which are used bythe firmware to control allow communication betweenthe firmwa

P R E L I M I N A R YAMD77Am79C930SIR0: General Configuration Register (GCR)This register is used to control general functions relatedto the Am79C93

AMDP R E L I M I N A R Y78Am79C9302 INT2EC 0 Interrupt to Embedded Controller. When INT2EC is set to a 1, aninterrupt is sent to the 80188 core. INT

P R E L I M I N A R YAMD79Am79C930SIR2: Local Memory Address Register [7:0] (LMA)This register is the beginning address on the local busfor system i

AMDP R E L I M I N A R Y8Am79C930Bus Interface Unit Interaction 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AMDP R E L I M I N A R Y80Am79C930SIR5: I/O Data Port B (IODPB)This register is a system interface I/O address alias ofI/O Data Port A.Bit Name Rese

P R E L I M I N A R YAMD81Am79C9304 PDC 0 Power Down Command. When PDC is set to 1, the power down cy-cle of the BIU power down state machine will

AMDP R E L I M I N A R Y82Am79C930MIR3: Power Down Length Count [15:8] (PDLC)This register is used to determine the length of powerdown cycles. Bef

P R E L I M I N A R YAMD83Am79C930MIR8: Flash Wait StatesThis register gives the Flash Wait states.Bit Name Reset Value Description 7:4 Reserved –

AMDP R E L I M I N A R Y84Am79C9306 Reserved – Reserved. Must be written as a 0. Reads of this bit produceundefined data.5:4 SRAMWAIT[1:0] 11b Thes

P R E L I M I N A R YAMD85Am79C930PCMCIA CCSR is RESET to a 0. If the STSCHGFN bit of TCR15has been set to a 0, then the value that is written to t

AMDP R E L I M I N A R Y86Am79C930Transceiver Attachment InterfaceRegisters (TIR Space)The Transceiver Attachment Interface (TAI) Unit con-tains a t

P R E L I M I N A R YAMD87Am79C930TIR mapping with SIR1 bit 2 (EIOW) set to “0” = normalTIR window mode. Note that EIOW = 0 is the only settingof EI

AMDP R E L I M I N A R Y88Am79C930TIR mapping with SIR1 bit 2 (EIOW) set to “1” = Ex-panded TIR window mode. Note that the settingEIOW = 1 is only a

P R E L I M I N A R YAMD89Am79C930TIR0: Network ControlGeneral control for the transceiver device attached tothe transceiver interface pins.Bit Nam

P R E L I M I N A R YAMD9Am79C930LED Support 73. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AMDP R E L I M I N A R Y90Am79C9301 RXDRQ 0 Receive FIFO DMA Request. This bit represents the currentvalue of the RXDRQ signal to the DRQ0 input of

P R E L I M I N A R YAMD91Am79C930The value read from SDD will always represent the current value ofthe SDDATA pin. The complete control of the fu

AMDP R E L I M I N A R Y92Am79C9305 MOREINT 1 MORE Interrupts. MOREINT will become set whenever there areinterrupt bits set in Interrupt Register 3

P R E L I M I N A R YAMD93Am79C930(Generated from the internal signal stop_d, which indicates that an-tenna diversity operation has selected an ante

AMDP R E L I M I N A R Y94Am79C930TIR8: Transmit ControlThis register is the Transmitter Control register.Bit Name Reset Value Description 7 TXRES

P R E L I M I N A R YAMD95Am79C930TIR9: Transmit StatusTransmit Status register. Indicates the current status ofthe Transmit portion of the TAI. Wr

AMDP R E L I M I N A R Y96Am79C930TIR11: Transmit Sequence ControlThis register is the Transmit Sequence Control. Thebits in this register determin

P R E L I M I N A R YAMD97Am79C930TIR12: Byte Count Register LSBThis register is the Byte count register LSB. This registercontains the lower 8 bits

AMDP R E L I M I N A R Y98Am79C930TIR15: Byte Count Limit MSBThis register is the Byte Count Limit MSB register. Bit Name Reset Value Description 7

P R E L I M I N A R YAMD99Am79C9305 RXFOR 0 Receive FIFO Overrun. This bit is set whenever the RX FIFO expe-riences an overrun. This bit is cleared