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Chapter 8 Signal and Power-Up Requirements 39

31993A-1 September 2004 AMD Sempron™ Processor Model 10 Data Sheet

AMD Preliminary Information

8 Signal and Power-Up Requirements

The AMD Sempron™ processor model 10 is designed to provide

functional operation if the voltage and temperature parameters

are within the limits of normal operating ranges.

8.1 Power-Up Requirements

Signal Sequence and

Timing Description

Figure 12 shows the relationship between key signals in the

system during a power-up sequence. This figure details the

requirements of the processor.

Figure 12. Signal Relationship Requirements During Power-Up Sequence

Notes: 1. Figure 12 represents several signals generically by using names not necessarily consistent

with any pin lists or schematics.

Requirements 1–8 in Figure 12 are described in “Power-Up Timing Requirements” on page 40.

3.3 V Supply

VCCA (2.5 V)

(for PLL)

RESET#

VCC_CORE

(Processor Core)

NB_RESET#

PWROK

System Clock

FID[3:0]

Warm reset

condition

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