AMD Duron Manual do Utilizador descarregar pdf (Página 23)

Chapter 4 Power Management 11

23802E—September 2000 AMD Duron™ Processor Data Sheet

Preliminary Information

any pending interrupts are recognized after returning to the

Normal state.

If RESET# is sampled asserted during the Stop Grant or Sleep

state, the processor immediately returns to the Full-on state

and the reset process begins.

Probe State The Probe state is entered when the system requires the

processor to service a probe. When in the Probe state, the

processor responds to a probe cycle in the same manner as

when it is in the Full-on state.

When the probe has been serviced, the processor returns to the

same state as when it entered the Probe state.

4.2 Connection and Disconnection Protocol

The AMD Duron processor enhances power savings in each of

the power management states when the system logic

disconnects the processor from the system bus and slows down

the internal clocks. Entering the lowest power state is

accomplished with a connection protocol between the processor

and system logic. The system can initiate a bus disconnection

upon the receipt of a Stop Grant special cycle. If required by the

system, the processor disconnects from the system bus and

slows down its internal clocks before entering the Stop Grant or

Sleep state. If the system requires the processor to service a

probe while it is in the Stop Grant state, it must first request

that the processor increase its clocks to full speed and

reconnect to the system bus. Table 1 on page 12 describes the

AMD Duron processor power states using the connection

protocol as described on page 12.

AMD system bus connections and disconnections are controlled

by an enable bit within the system controller.

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