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34 Signal and Power-Up Requirements Chapter 7

AMD Duron™ Processor Data Sheet 23802E—September 2000

Preliminary Information

6. NB_RESET# should be asserted (causing CONNECT to also

assert) before RESET# is deasserted.

If NB_RESET# does not assert until after RESET# has

deasserted, the processor misinterprets the CONNECT

assertion (due to NB_RESET# being asserted) as the

beginning of the SIP transfer (See “Serial Initialization

Packet (SIP) Protocol” on page 34). There must be sufficient

overlap in the resets to ensure that CONNECT has a chance

to be sampled asserted by the processor in advance of the

processor coming out of reset.

Clock Multiplier

Selection (FID[3:0])

When RESET# is deasserted, the processor selects the

processor clock ratio (multiplier) by driving the FID[3:0]

signals. The system samples the clock multiplier value from

FID[3:0]. For more information, see “FID[3:0] Pins” on page 58.

The system samples the processor clock multiplier value and

other system configuration information when RESET#

deasserts, and uses this value to correctly initialize and

configure the system bus. The system sends the processor its

initialization state in a serial packet using the Serial

Initialization Packet (SIP) protocol. This protocol uses the

PROCRDY, CONNECT, and CLKFWDRST signals, which are

synchronous to SYSCLK.

Serial Initialization Packet (SIP) Protocol. Figure 11 on page 35 shows

the protocol for a typical SIP transfer to the processor after

reset. Table 16 on page 35 describes the requirements for the

SIP transfer from the system to the processor. Processors and

Northbridges are designed to adhere to the following protocol

and do not require motherboard intervention.

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AMD Duron Manual do Utilizador Página 46