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58 Pin Descriptions Chapter 9

AMD Duron™ Processor Data Sheet 23802E—September 2000

Preliminary Information

FERR Pin FERR is an output to the system that is asserted for any

unmasked numerical exception independent of the NE bit in

CR0. FERR is an open-drain active High signal that must be

inverted and level shifted to an active Low signal that is 3.3V

when deasserted. For more information about FERR and

FERR#, see the “Required Circuits” chapter of the

Motherboard PGA Design Guide, order# 90009.

FID[3:0] Pins See “Frequency Identification (FID[3:0])” on page 20 for the

AC and DC characteristics for FID[3:0].

FID[3] (Y3), FID[2] (Y1), FID[1] (W3), and FID[0] (W1) are the

4-bit processor clock to SYSCLK ratio. Table 20 describes the

encodings of the clock multipliers on FID[3:0].

Table 20. FID[3:0] Clock Multiplier Encodings

FID[3] FID[2] FID[1] FID[0]

Processor Clock to

SYSCLK Frequency

Ratio

0000 11

0001 11.5

0010 12

0011 >= 12.5

0100 5

0101 5.5

0110 6

0111 6.5

1000 7

1001 7.5

1010 8

1011 8.5

1100 9

1101 9.5

1110 10

1111 10.5

Note:

All ratios greater than or equal to 12.5x have the same FID[3:0] code of 0011, which causes

the SIP configuration for all ratios of 12.5x or greater to be the same.

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AMD Duron Manual do Utilizador Página 70