AMD Duron Manual do Utilizador Página 48

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36 Signal and Power-Up Requirements Chapter 7
AMD Duron Processor Data Sheet 23802ESeptember 2000
Preliminary Information
7.2 Processor Warm Reset Requirements
The AMD Duron
Processor and
Northbridge Reset
Pins
Warm resets differ from cold resets because the motherboard
power supplies are already stable and the processor PLL is
locked. Requirements differ for warm resets because the
AMD Duron processor may be in a system sleep state when
RESET# asserts.
Duration of RESET# As a Function Of Low Power Ratio. Although the
processor PLL is already locked, the processor requires that
RESET# be asserted for some period to ensure that PROCRDY
can assert without glitching.
The AMD Duron processor clock grid is slowed down to a ratio
of as little as 1/128th of its normal frequency. Therefore, it takes
a corresponding length of time to assert PROCRDY. In addition,
in order to avoid glitching PROCRDY, it is necessary to assert
RESET# for a duration that the AMD Duron processor can
synchronize RESET# into the processor clock domain.
Table 17 shows the minimum RESET# duration to ensure the
proper PROCRDY pin behavior as a function of the low power
ratio.
Assertion of RESET# to Deassertion of NB_RESET#. When the
Northbridge exits reset, the processor must have PROCRDY
asserted in response to the RESET# assertion or else the
Northbridge may start the SIP transfer (because some
Northbridges sample only for a Low PROCRDY level). This
scenario implies a dependency from RESET#=0 to
NB_RESET#=1:
Table 17. RESET# Minimum Duration
Processor Version
Low Power Divisor
(recommended)
RESET#
Min assertion time
AMD Duron processor 128 2.5
µs @100MHz SYSCLK
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