AMD Duron Manual do Utilizador descarregar pdf (Página 45)

Chapter 7 Signal and Power-Up Requirements 33

23802E—September 2000 AMD Duron™ Processor Data Sheet

Preliminary Information

Timing Requirements. The signal timing requirements are as

follows:

1. RESET# must be asserted before PWROK is asserted

The AMD Duron processor does not set the correct clock

multiplier if PWROK is asserted prior to a RESET#

assertion. It is recommended that RESET# be asserted at

least 10ns

prior to the assertion of PWROK.

2. All motherboard power supplies should be ramped before

the assertion of PWROK.

The processor core voltage, VCC_CORE, should have a

stable voltage (for example, 1.7V) as indicated by the

Voltage ID (VID) prior to PWROK assertion. Before PWROK

assertion, the AMD Duron processor is clocked by a ring

oscillator. This minimum time is not specified.

The AMD Duron processor PLL is powered by VCCA. The

processor PLL does not lock if VCCA is not high enough for

the processor logic to switch for some period before PWROK

is asserted. The recommended minimum time before

PWROK assertion is 5

µs.

3. The system clock (SYSCLK/SYSCLK#) should be running

before PWROK is asserted.

When PWROK is asserted, the AMD Duron processor

switches from driving the internal processor clock grid from

the ring oscillator to driving from the PLL. The reference

system clock should be valid at this time. If it is not valid,

the subsequent requirements may be undermined. It is

recommended that PWROK be asserted 3ms after the

system clocks are running.

4. PWROK assertion to deassertion of RESET#

The duration of reset during cold boots is intended to

satisfy the time it takes for the PLL to lock with a less than

1-ns phase error. The AMD Duron processor PLL begins to

run after PWROK is asserted and the internal clock grid is

switched from the ring oscillator to the PLL. The PLL lock

time may take from hundreds of nanoseconds to tens of

microseconds. It is recommended that the minimum time

between PWROK assertion to the deassertion of RESET# be

at least 1.5ms.

5. PWROK should be monotonic.

The processor should not switch between the ring oscillator

and the PLL after the initial assertion of PWROK.

1 2 ... 40 41 42 43 44 45 46 47 48 49 50 ... 83 84

Comentários a estes Manuais

Sem comentários

AMD Duron Manual do Utilizador Página 45

Comentários a estes Manuais

Manuais e produtos relacionados com Processadores AMD Duron