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12 Power Management Chapter 4
AMD Duron™ Processor Data Sheet 23802E—September 2000
Preliminary Information
Connection Protocol In addition to the legacy STPCLK# signal and the Halt and Stop
Grant special cycles, the AMD system bus connection protocol
includes the CONNECT, PROCRDY, and CLKFWDRST signals
and a Connect special cycle.
AMD system bus disconnects are initiated by the system
controller in response to the receipt of a Stop Grant special
cycle. Reconnections are initiated by the processor in response
to an interrupt or STPCLK# deassertion, or by the system to
service a probe.
A disconnect request is implicit, if enabled, in the processor
Stop Grant special cycle request. It is expected that the system
Table 1. AMD Duron™ Processor Power Management States
State Name Entered Exited
Full-On / Normal
This is the full-on running state of the
processor
Initiates either a Halt instruction or STPCLK#
assertion.
Halt
Execution of the Halt instruction. A special
cycle is issued. The processor may enter a
lower power state.
The processor exits and returns to the Run state upon
the occurrence of INIT#, INTR, NMI, SMI# or RESET#.
The processor transitions to the Stop Grant state if
STPCLK# is asserted and returns to the Halt state
upon STPCLK# deassertion.
Stop Grant
The processor transitions to the Stop Grant
state with the assertion of STPCLK# (as a
result of a read to the PLVL_2 register). A
Stop Grant special cycle is issued. The
processor may enter a lower power state.
Note: While in this state, interrupts are
latched and serviced when the processor
transitions to the Full-on state.
The processor transitions to the Full-on or Halt state
upon STPCLK# deassertion.
RESET# asserted initializes the processor but, if
STPCLK# is asserted, the processor returns to the
Stop Grant state.
Probe
A transition to the Probe state occurs when
the system asserts CONNECT. The
processor remains in this state until the
probe is serviced and any data is
transferred.
The processor returns to the Halt or Stop Grant state
when the probe has been serviced and the system
deasserts CONNECT. If the processor was
disconnected from the bus in the previous state, bus
disconnection occurs and the internal frequency of
the processor is again slowed down.
Sleep
The processor can enter its lowest power
state, Sleep, from the Full-on state with the
assertion of STPCLK# (as a result of a read
to the PLVL_3 register).
Note: While in this state, interrupts are
latched and serviced when the processor
transitions to the Full-on state.
The processor transitions to the Run state upon
STPCLK# deassertion. Asserting RESET# initializes the
processor but, if STPCLK# is asserted, the processor
returns to the Sleep state.
- AMD Duron 1
- Contents 3
- Contents v 5
- List of Figures 7
- List of Tables 9
- Preliminary Information 10
- Revision History 11
- 1 Overview 13
- 23802E—September 2000 14
- 4 Overview Chapter 1 16
- 2 Interface Signals 17
- 2.3 Push-Pull (PP) Drivers 18
- 2.4 AMD System Bus Signals 18
- 3 Logic Symbol Diagram 19
- 4 Power Management 21
- CLKFWDRST 26
- 5 Thermal Design 29
- 18 Thermal Design Chapter 5 30
- 6 Electrical Data 31
- VCCA-NOISE 33
- 6.8 Absolute Ratings 34
- 6.9 Power Dissipation 34
- = 400mV V 35
- 24 Electrical Data Chapter 6 36
- Figure 9. SYSCLK Waveform 36
- SKEW-SAMEEDGE 38
- SKEW-DIFFEDGE 38
- Chapter 6 Electrical Data 29 41
- 30 Electrical Data Chapter 6 42
- 7.1 Power-Up Requirements 43
- 8 Mechanical Data 49
- 38 Mechanical Data Chapter 8 50
- Measurements are in mm 51
- 40 Mechanical Data Chapter 8 52
- 9 Pin Descriptions 53
- AMD Duron™ Processor 54
- Topside View 54
- Chapter 9 Pin Descriptions 43 55
- 44 Pin Descriptions Chapter 9 56
- Chapter 9 Pin Descriptions 45 57
- 46 Pin Descriptions Chapter 9 58
- Chapter 9 Pin Descriptions 47 59
- 48 Pin Descriptions Chapter 9 60
- 9.2 Pin List 61
- 50 Pin Descriptions Chapter 9 62
- Chapter 9 Pin Descriptions 51 63
- 52 Pin Descriptions Chapter 9 64
- Chapter 9 Pin Descriptions 53 65
- 54 Pin Descriptions Chapter 9 66
- Chapter 9 Pin Descriptions 55 67
- 56 Pin Descriptions Chapter 9 68
- 9.3 Detailed Pin Descriptions 69
- 64 Pin Descriptions Chapter 9 76
- 10 Ordering Information 77
- Appendix A 79
- Conventions, Abbreviations 79
- Data Terminology 80
- Abbreviations and Acronyms 81
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