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Chapter 4 Power Management 13

23802E—September 2000 AMD Duron™ Processor Data Sheet

Preliminary Information

controller provides a BIOS-programmable register in which it

can disconnect the processor from the AMD system bus upon

the occurrence of a Stop Grant special cycle. The system

receives the special cycle request from the processor and, if

there are no outstanding probes or data movements, the system

deasserts CONNECT to the processor. The processor detects the

deassertion of CONNECT on a rising edge of SYSCLK, and

deasserts PROCRDY to the system. In return, the system

asserts CLKFWDRST in anticipation of reestablishing a

connection at some later point.

Note: The system must disconnect the processor from the

AMD system bus before issuing the Stop Grant special cycle

to the PCI bus.

The processor can receive an interrupt or STPCLK# deassertion

after it sends a Stop Grant special cycle to the system but

before the disconnection actually occurs. In this case, the

processor sends the Connect special cycle to the system, rather

than continuing with the disconnect sequence. The system

cancels the disconnection. Figure 4 shows the sequence of

events from a system perspective, which leads to disconnecting

the processor from the AMD system bus and placing the

processor in the Stop Grant state.

Figure 4. Example System Bus Disconnection Sequence

The following sequence of events describes how the processor is

placed in the Stop Grant state when bus disconnection is

enabled within the system controller:

1. The peripheral controller asserts STPCLK# to place the

processor in the Stop Grant state.

2. When the processor receives STPCLK#, it acknowledges the

system by sending out a Stop Grant special bus cycle on the

AMD system bus.

Stop Grant SBC

STPCLK#

CONNECT

PROCRDY

CLKFWDRST

PCI Bus

System Bus

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