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AMD-K5 Processor Data Sheet 18522F/0—Jan1997

PRELIMINARY INFORMATION

4 Architectural Introduction

The x86 architecture is the dominant standard for the personal

computer marketplace. However, maintaining backwards com-

patibility with previous generations of x86 processors carries

several inherent limitations associated with the x86 architec-

ture: variable-length instruction set, fewer general-purpose

registers, and complex addressing modes. The AMD-K5 proces-

sor overcomes these burdens by providing superscalar archi-

tecture that incorporates innovative technology: instruction

predecoding, improved cache architecture, branch prediction

with speculative execution, a superscalar RISC core, out-of-

order execution, and register renaming.

4.1 Superscalar RISC Core

The AMD-K5 processor’s superscalar RISC core consists of six

execution units: two arithmetic logic units (ALU), two load/

store units, one branch unit, and one floating-point unit (FPU).

This superscalar core is fully decoupled from the x86 bus

through the conversion of variable-length x86 instructions into

simple, fixed-length RISC operations (ROPs) that are easier to

handle and execute faster. Once the x86 instruction has been

converted, a dispatcher issues four ROPs at a time to the

superscalar core. The processor’s superscalar core can execute

at a peak rate of six ROPs per cycle. The superscalar core sup-

ports data forwarding and data bypassing to immediately for-

ward the results of an execution to successive instructions.

This eliminates the delay of writing the results to output regis-

ters or memory and reading them back to the instruction need-

ing the results.

4.2 Out-of-Order Execution

The AMD-K5 processor implements out-of-order execution to

eliminate delays due to pipeline dependencies. Each execution

unit has two reservation stations that hold ROPs prior to exe-

cution (except the FPU, which has one reservation station).

ROPs can be issued out of order from the reservation stations

and executed out of order. Some execution units will empty

their reservation stations before others. Since each execution

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