AMD K5 Manual do Utilizador Página 7
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18522F/0—Jan1997 AMD-K5 Processor Data Sheet
PRELIMINARY INFORMATION
List of Figures
Figure 1. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. Logic Symbol Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 3. State Transition Diagram for Stop Clock State Machine. . . . . 29
Figure 4. Bus State Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 5. Single Writes (Zero Wait States) . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 6. Burst Write (One Wait State) . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 7. BOFF
Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 8. Locked Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 9. HOLD/HLDA Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 10. Interrupt Acknowledge Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 11. Inquire Cycle (Hit to a Non-Modified Line) . . . . . . . . . . . . . . . 46
Figure 12. Inquire Cycle (Hit to a Modified Line) . . . . . . . . . . . . . . . . . . . 46
Figure 13. Pipelined Cacheable Data Cache Cycle into
a Cacheable Instruction Cache Cycle. . . . . . . . . . . . . . . . . . . . . 49
Figure 14. Pipelined Write Cycle (Could be I/O) into
a Write Cycle (Could be I/O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 15. Diagrams Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 16. CLK Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 17. Output Valid Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 18. Input Setup and Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 19. Maximum Float Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 20. Reset and Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 21. TCK Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 22. TRST
Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 23. Test Signal Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 24. STPCLK
Timing (Stop Grant state) . . . . . . . . . . . . . . . . . . . . . . 72
Figure 25. Transition L1 Shared Line to Exclusive. . . . . . . . . . . . . . . . . . . 72
Figure 26. Invalidation to Non-Modified L1 Cache Line . . . . . . . . . . . . . . 73
Figure 27. Invalidation to Modified Line in
L1 Cache (Writeback Cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 28. Single Read due to CACHE
Inactive (No Wait State) . . . . . . . 74
Figure 29. Single Read due to KEN
Not Asserted (One Wait State). . . . . 74
Figure 30. Single Write due to KEN
Inactive (No Wait State) . . . . . . . . . 75
Figure 31. Single Write due to CACHE
Inactive (One Wait State). . . . . . 75
Figure 32. Burst Read (No Wait State). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 33. Burst Read (One Wait State). . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 34. Burst Write (One Wait State) . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 35. BOFF
Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 36. Locked Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 37. HOLD/HLDA Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 38. AHOLD Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 39. Special Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 40. Interrupt Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
- Data Sheet 1
- Trademarks: 2
- Contents 3
- 10.4 RESET, TCK, TRST 6
- List of Figures 7
- List of Tables 9
- 18522F/0—Jan1997 10
- PRELIMINARY INFORMATION 10
- 1 AMD-K5™ Processor Features 11
- 1.2 High-Performance Design 12
- 1.3 Compatibility 12
- Revision History 13
- 2 Block Diagram 14
- 3 Ordering Information 15
- 4 Architectural Introduction 16
- 4.3 Register Renaming 17
- 4.6 Cache Architecture 18
- 4.7 Branch Prediction 19
- 4.9 Reorder Buffer 20
- 4.10 Register File 21
- 5 CPU Identification 22
- 6 Logic Symbol Diagram 23
- 7 Signal Descriptions 24
- AMD-K5 Processor Data Sheet 35
- Table 2. Output Pins 35
- Table 3. Input/Output Pins 36
- Table 4. Test Pins 36
- Table 5. Bus Cycle Definition 36
- Table 6. Special Cycles 37
- 8 Processor Operation 38
- 8.3 Cache Protocol 41
- 8.4 Data Cache Coherency 42
- 8.5 External Bus Description 46
- 8.6 Bus Cycles 48
- 8.7 System Management Mode 61
- Table 12. SMM Save Area Map 62
- 8.8 Am486 64
- 9 Electrical Data 66
- 9.2 Absolute Maximum Ratings 67
- 9.3 Operating Ranges 67
- 10 Switching Characteristics 69
- 10.2 60-MHz Bus Operation 72
- 10.3 50-MHz Bus Operation 74
- Figure 15. Diagrams Key 78
- Figure 16. CLK Waveform 78
- Figure 21. TCK Waveform 81
- Figure 22. TRST Timing 81
- 11 Timing Diagrams 82
- Figure 39. Special Cycle 89
- Start blank 90
- 13 Physical Dimensions 94
- 15 Pin Designations (Model 0) 96
- Functional Grouping 98
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