AMD K5 Manual do Utilizador descarregar pdf (Página 64)

AMD-K5 Processor Data Sheet 18522F/0—Jan1997

PRELIMINARY INFORMATION

unpredictable if the I/O instruction restart word is written

when the processor has not generated an SMI on an I/O instruc-

tion boundary. The SMI handler for the second request must

not set the I/O instruction restart word if the system executes

back-to-back SMI requests.

Halt Auto Restart On entry to the SMI routine, the Halt Auto Restart word

(FF02h) has the value 0001h if the processor was halted when

the SMI occurred. Otherwise, it has a value of 0000h.

If the value is 0001h, the SMI routine may cause a return to the

HALT instruction by returning without modifying the Halt

Auto Restart word. It may cause a return to the instruction

after the halt instruction by clearing the Halt Auto Restart

word.

8.8 Am486

and AMD-K5 Processor Bus Differences

The AMD-K5 processor:

■ Data bus is 64 bits, versus the Am486 processor’s 32 bits

■ Has eight byte-enables and eight data parity pins

■ Does not support non-cacheable burst cycles

■ Supports FLUSH as an edge-triggered input

■ Supports a writeback cache protocol using MESI (The new

CACHE, HIT, HITM, WB/WT, and INV pins are defined to

support this protocol.)

■ Maintains the state of the internal caches and FPU, while

performing the reset function with the INIT pin

■ Supports SMM with the input signal SMI and the output sig-

nal SMIACT

■ Does not allow invalidations every clock or while driving

the address bus

■ Supports parity checking on addresses and data

■ Does not support dynamic bus sizing. This eliminates the

need for the Am486 processor signals BS8 and BS16

■ Includes the SCYC signal to indicate a split cycle during

locked operations. A split cycle crosses a cache line bound-

ary during an atomic operation due to a misaligned refer-

ence

1 2 ... 59 60 61 62 63 64 65 66 67 68 69 ... 99 100

Sem comentários

AMD K5 Manual do Utilizador Página 64