AMD K5 Manual do Utilizador descarregar pdf (Página 47)

18522F/0—Jan1997 AMD-K5 Processor Data Sheet

PRELIMINARY INFORMATION

Figure 4. Bus State Transitions

Memory

Organization

Physical memory address space ranges from 0000_0000h to

FFFF_FFFFh. Memory space is organized in 64-bit sections.

Each 64-bit section has 8 bytes at consecutive memory

addresses. The first address of each group is evenly divisible

by 8, and each group is addressed by A31–A3. Since the proto-

col does not implement A2–A0 when interfacing to 32-bit, 16-

bit, or 8-bit memories, the lower portions of the address must

be determined by decoding the eight byte-enable signals. The

address space of I/O begins at 0000_0000h and ends at

0000_FFFFh. I/O space is organized as a sequence of 8-bit

quantities.

idle

address

ready

No Request

Pending

The processor always goes to T

ready

and processes the data transfer.

The processor will remain in T

until the transfer is completed.

Request Pending

The last BRDY. Finish the current cycle

and return to the idle state. If LOCK

is asserted, and a non-cacheable read

is followed by a non-cacheable write,

an idle cycle is generated during

which LOCK is negated.

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AMD K5 Manual do Utilizador Página 47