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AMD-K5 Processor Data Sheet 18522F/0—Jan1997

PRELIMINARY INFORMATION

Table 16. Delay Timing for 66-MHz Bus Operation

Symbol Parameter Description

Advance Info

Figure Comments

Min Max

ADSC, PWT, PCD, CACHE, SCYC Valid Delay 1.0 ns 7.0 ns 17

AP Valid Delay 1.0 ns 8.5 ns 17

A31–A17 Valid Delay 0.6 ns 6.3 ns 17

A16–A3 Valid Delay 0.5 ns 6.3 ns 15

ADS Valid Delay 1.0 ns 6.0 ns 17

BE7–BE0 Valid Delay 0.9 ns 7.0 ns 15

LOCK Valid Delay 0.9 ns 7.0 ns 15

M/IO Valid Delay 0.8 ns 5.9 ns 15

D/C, W/R Valid Delay 0.8 ns 7.0 ns 15

ADS, ADSC, AP, A31–A3, BE7–BE0, CACHE, D/C, LOCK,

M/IO

, PWT, PCD, SCYC, W/R Float Delay

10.0 ns 19

APCHK, IERR, FERR Valid Delay 1.0 ns 8.3 ns 17

PCHK Valid Delay 1.0 ns 7.0 ns 17

BREQ, HLDA Valid Delay 1.0 ns 8.0 ns 17

SMIACT Valid Delay 1.0 ns 7.3 ns 17

10a

HIT Valid Delay 1.0 ns 6.8 ns 17

10b

HITM Valid Delay 0.7 ns 6.0 ns 17

PRDY Valid Delay 1.0 ns 8.0 ns 17

D63–D0, DP7–DP0 Write Data Valid Delay 1.3 ns 7.5 ns 17

D63–D0, DP7–DP0 Write Data Float Delay 10.0 ns 19

1 2 ... 65 66 67 68 69 70 71 72 73 74 75 ... 99 100

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AMD K5 Manual do Utilizador Página 70