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AMD-K5 Processor Data Sheet 18522F/0—Jan1997

PRELIMINARY INFORMATION

10.4 RESET, TCK, TRST, and Test Signal Timing

Table 24. RESET Configuration Signal

Symbol Parameter Description

Advance Info

Figure Comments

Min Max

RESET Setup Time 5.0 ns 20

RESET Hold Time 1.0 ns 20

RESET Pulse Width, V

and CLK stable

15 clocks 20

RESET active after V

and CLK stable

1.0 ms 20

INIT, FLUSH, FRCMC Setup Time 5.0 ns 20

INIT, FLUSH, FRCMC Hold Time 1.0 ns 20

42a

INIT, FLUSH, FRCMC Setup Time 2 clocks 20 Asynchronous, Note 1

42b

INIT, FLUSH, FRCMC, BRDYC,

BUSCHK

Hold Time

2 clocks 20 Asynchronous, Note 1

42c

BRDYC, BUSCHK Setup Time 3 clocks 20 Note 1

42d

BRDYC Hold Time, RESET driven synchronously 1.0 ns 20 Note 1

43a

BF, BF0, BF1 Setup Time 1.0 ms 20 Note 1

43b

BF, BF0, BF1 Hold Time 2 clocks 20 Note 1

Notes:

1. These are measured to RESET falling edge.

Table 25. TCK Waveform and TRST Timing at 16 MHz

Symbol Parameter Description

Advance Info

Figure Comments

Min Max

TCK Frequency 16 MHz 1X Clock

TCK Period 62.5 ns 21 Note 1

TCK High Time 25.0 ns 21 at 2.0 V, Note 3

TCK Low Time 25.0 ns 21 at 0.8 V, Note 3

TCK Fall Time 5.0 ns 21 Notes 2, 3

TCK Rise Time 5.0 ns 21 Notes 2, 3

TRST Pulse Width 40.0 ns 22 Asynchronous

Notes:

1. TCK period is ≥ CLK period.

2. Rise/Fall times are measured between 0.8 V and 2.0 V. Rise/Fall times can be relaxed by 1 ns per 10-ns increase in TCK period.

3. Not 100% tested; determined by design characterization.

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