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18522F/0—Jan1997 AMD-K5 Processor Data Sheet

PRELIMINARY INFORMATION

10 Switching Characteristics

The AMD-K5 processor commercial switching characteristics,

provided in Table 15 through Table 26 on page 67, are mea-

sured at the voltage levels indicated by Figure 16 on page 68.

They are measured relative to the rising edge of the CLK sig-

nal, as defined by Figure 16 through Figure 23. Output delays

are specified as a function of minimum and maximum limits,

with minimum delay times provided to external circuitry as

hold times. A synchronous input signal must be stable for cor-

rect AMD-K5 processor operation during sampling.

10.1 66-MHz Bus Operation

Table 15. CLK Switching Characteristics for 66-MHz Bus Operation

Symbol Parameter Description

Advance Info

Figure Comments

Min Max

Frequency 33.3 MHz 66.6 MHz

CLK Period 15 ns 30.0 ns 16

CLK Period Stability ± 250 ps Note 1

CLK High Time 4.0 ns 16 @ 2.0 V, Note 1

CLK Low Time 4.0 ns 16 @ 0.8 V, Note 1

CLK Fall Time 0.15 ns 1.5 ns 16 2.0–0.8 V, Note 1

CLK Rise Time 0.15 ns 1.5 ns 16 0.8–2.0 V, Note 1

Notes:

1. Not 100% tested; determined by design characterization.

1 2 ... 64 65 66 67 68 69 70 71 72 73 74 ... 99 100

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AMD K5 Manual do Utilizador Página 69