AMD K5 Manual do Utilizador Página 5
- Página / 100
- Índice
- MARCADORES
Avaliado. / 5. Com base em avaliações de clientes
v
18522F/0—Jan1997 AMD-K5 Processor Data Sheet
PRELIMINARY INFORMATION
Internal Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Cacheability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Copy-Back Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8.4 Data Cache Coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Cache Invalidation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Read Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Write Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Write Allocate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
External Inquire Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Instruction Cache Coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Self-Modifying Code and the Cache . . . . . . . . . . . . . . . . . . . . . 36
8.5 External Bus Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
8.6 Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Single Transfer Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Burst Read Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Burst Write Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
BOFF
or AHOLD/HOLD/HLDA During Burst Transfers . . . . . 40
Use of BOFF
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Locked Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
LOCK
during HOLD and BOFF . . . . . . . . . . . . . . . . . . . . . . . . . 42
LOCK
Operations during Inquire Cycles . . . . . . . . . . . . . . . . . 42
Locked Operation to Cached Lines . . . . . . . . . . . . . . . . . . . . . . 43
Bus Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Bus Error Support using PCHK
and APCHK . . . . . . . . . . . . . . 44
Special Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Flush Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Interrupt Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Inquire Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Pipelining Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
8.7 System Management Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Processing System Management Interrupts . . . . . . . . . . . . . . . 51
System Management Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . 51
Initial State Upon Entering SMM . . . . . . . . . . . . . . . . . . . . . . . 53
I/O Instruction Restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Halt Auto Restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
8.8 Am486
®
and AMD-K5 Processor Bus Differences . . . . . . . . . . 54
8.9 P54C and AMD-K5 Processor Bus Differences . . . . . . . . . . . . . 55
9 Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
9.1 Power and Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Power Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Connection Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . 56
9.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
9.3 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Commercial (C) Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
- Data Sheet 1
- Trademarks: 2
- Contents 3
- 10.4 RESET, TCK, TRST 6
- List of Figures 7
- List of Tables 9
- 18522F/0—Jan1997 10
- PRELIMINARY INFORMATION 10
- 1 AMD-K5™ Processor Features 11
- 1.2 High-Performance Design 12
- 1.3 Compatibility 12
- Revision History 13
- 2 Block Diagram 14
- 3 Ordering Information 15
- 4 Architectural Introduction 16
- 4.3 Register Renaming 17
- 4.6 Cache Architecture 18
- 4.7 Branch Prediction 19
- 4.9 Reorder Buffer 20
- 4.10 Register File 21
- 5 CPU Identification 22
- 6 Logic Symbol Diagram 23
- 7 Signal Descriptions 24
- AMD-K5 Processor Data Sheet 35
- Table 2. Output Pins 35
- Table 3. Input/Output Pins 36
- Table 4. Test Pins 36
- Table 5. Bus Cycle Definition 36
- Table 6. Special Cycles 37
- 8 Processor Operation 38
- 8.3 Cache Protocol 41
- 8.4 Data Cache Coherency 42
- 8.5 External Bus Description 46
- 8.6 Bus Cycles 48
- 8.7 System Management Mode 61
- Table 12. SMM Save Area Map 62
- 8.8 Am486 64
- 9 Electrical Data 66
- 9.2 Absolute Maximum Ratings 67
- 9.3 Operating Ranges 67
- 10 Switching Characteristics 69
- 10.2 60-MHz Bus Operation 72
- 10.3 50-MHz Bus Operation 74
- Figure 15. Diagrams Key 78
- Figure 16. CLK Waveform 78
- Figure 21. TCK Waveform 81
- Figure 22. TRST Timing 81
- 11 Timing Diagrams 82
- Figure 39. Special Cycle 89
- Start blank 90
- 13 Physical Dimensions 94
- 15 Pin Designations (Model 0) 96
- Functional Grouping 98
Manuais e produtos relacionados com Processadores AMD K5
(60 páginas)© 2020, manymanuals-pt.com. Todos os direitos reservados. | 0.073 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Comentários a estes Manuais