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AMD-K5 Processor Data Sheet 18522F/0—Jan1997

PRELIMINARY INFORMATION

The AMD-K5 processor uses the MESI protocol—2 bits per

cache line—in its data cache to ensure consistency in multipro-

cessing systems. The physical tags of both the instruction and

data cache are accessed and compared during each inquire

cycle to maintain a consistent copy of data.

Cacheability The PCD and PWT bits in the page directory and page-table

entry control caching on a page-by-page basis. The PCD and

PWT bits manage page caching and drive processor PCD and

PWT output pins.

PCD affects the cacheability of pages in the internal cache.

The PWT bit determines whether the writethrough or write-

back policy is used for this particular page.

Copy-Back Buffers A one-line copy-back buffer is employed within the AMD-K5

processor to temporarily hold a modified entry being replaced

in the data cache. The replaced line is stored in the copy-back

buffer at the same time the read request for the replacement

line is sent externally. Following completion of the read

access, the modified line in the copy-back buffer is written

back to memory. The copy-back buffer is snooped during

inquire cycles.

A requested-word-first protocol is implemented by the

AMD-K5 processor. Following receipt of the first data item,

execution continues while the following three entries of the

line are being fetched. The line is not marked valid until the

last entry is stored in the cache.

8.4 Data Cache Coherency

Throughout this discussion, the MESI states may be abbrevi-

ated as follows:

M—Modified Exclusive State

E—Exclusive State

S—Shared State

I—Invalid State

Cache Invalidation FLUSH writes back all modified lines and then invalidates all

cache lines and generates a Flush Acknowledge special cycle

to instruct the L2 cache to invalidate all lines.

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