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18522F/0—Jan1997 AMD-K5 Processor Data Sheet

PRELIMINARY INFORMATION

8.7 System Management Mode

System Management Mode (SMM) is a distinct processor

mode—initiated by SMI—that allows the system designer to

add software-controlled features that operate transparently to

the operating system and application programs, such as power

management. I/O Restart and Halt Auto-Restart are also pro-

vided for transparent power management of I/O peripherals.

The system designer may use the SMIACT signal to provide

protection to the SMI handler code and CPU state information.

Processing System

Management

Interrupts

When the processor receives an SMI, normal operation will be

interrupted in the following manner:

1. SMIACT is asserted, informing the system that it must

enable the SMRAM.

2. Once SMRAM is available, the processor saves its state

beginning at 3FFFFh. The save area map is provided in

Table 12 (given that the default SMIBASE is 30000h).

3. Once the normal execution state is saved in SMRAM, the

processor enters SMM.

4. The processor will jump to SMRAM address 38000h to exe-

cute the SMI handler, which will perform any required sys-

tem management.

5. When the Resume (RSM) instruction is received, the SMI

handler restores the processor normal execution state from

SRAM, negate the SMIACT signal, and resume execution.

System Management

Interrupt

SMI is triggered on a clock falling edge. It is non-maskable and

may be asserted asynchronously, but it will be recognized in

the first cycle meeting set-up and hold times. To assure asyn-

chronous recognition, SMI should be asserted for at least two

clocks and negated for at least two clocks.

SMI interrupts occur on instruction boundaries. SMI is not

affected by the IF bit in the EFLAGS register. The SMI signal

will be masked internally when the SMI is recognized until the

RSM instruction is executed. SMI has a higher priority than

NMI. It is not masked during an NMI. (See Figure 41 on page

80.)

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