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AMD-K5 Processor Data Sheet 18522F/0—Jan1997

PRELIMINARY INFORMATION

Normal Execution

State

In this state, the AMD-K5 processor operates at full speed. All

clocks are running.

Halt/Auto-Power-

Down State

In this state, most internal clocks are stopped. The Phase Lock

Loop (PLL) is operating and certain bus interface components

are clocked. Instruction execution is disabled. This aids in

timely detection of inquire cycles and HOLD/HLDA sequences,

while greatly reducing power consumption.

The Halt/Auto-Power-Down State is entered from normal exe-

cution state by executing the HALT instruction in Real mode

or Protected mode. The clock state will return to normal execu-

tion state when an interrupt, non-maskable interrupt, system

management interrupt, power-on reset, or soft reset is detected

(INTR, NMI, SMI, RESET, or INIT, respectively). The clock

state may temporarily transition from Halt/Auto-Power-Down

State to Stop Clock Snoop State to process an inquire cycle or

to Stop Grant State in response to a STPCLK. In these cases,

the clock state will return to Halt/Auto-Power-Down State and

wait for one of the interrupt conditions when the secondary

condition is removed.

Stop Grant State In this state, most internal clocks are stopped. The PLL is oper-

ating and certain bus interface components are clocked.

Instruction execution is disabled. This allows timely detection

of inquire cycles and HOLD/HLDA sequences, while greatly

reducing power consumption.

The Stop Grant State is entered from Normal Execution State

or Halt/Auto-Power-Down State by asserting the STPCLK pin.

When STPCLK is sampled as asserted, the current instruction

is completed, all processing is stopped, a Stop Grant bus cycle

is generated, and the clock is shut down. The clock state will

return to its previous state when STPCLK is negated. Once

asserted, STPCLK must not be negated until the Stop Grant

Acknowledge special cycle is seen. The clock state may tempo-

rarily transition from Stop Grant State to Stop Clock Snoop

State to process an inquire cycle, or to Stop Clock State to pro-

cess a Stop Clock request. In these cases, the clock state will

return to Stop Grant State when the secondary condition is

removed.

STPCLK is treated as the lowest priority external interrupt. If

a higher priority external interrupt exists (power-on reset, soft

reset, flush, system management interrupt, non-maskable

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