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18522F/0—Jan1997 AMD-K5 Processor Data Sheet

PRELIMINARY INFORMATION

R/S Run/STOP Input

The R/S signal provides an edge-sensitive interrupt to stop nor-

mal execution. A falling-edge transition halts execution at the

next instruction boundary. A rising-edge transition, which

must not occur before PRDY is asserted, resumes execution.

SCYC Split Cycle Output

SCYC indicates split cycles when LOCK is asserted. This signal

indicates that more than two cycles will be locked together for

misaligned locked transfers.

SMI System Management Interrupt Input

SMI allows external logic to request a non-maskable system

management interrupt. Asserting this signal will cause the pro-

cessor to suspend normal execution and enter System Manage-

ment Mode (SMM) at the next instruction boundary.

SMIACT SMI Active Output

SMIACT is asserted when the processor is operating in SMM.

STPCLK Stop Clock Input

STPCLK, when asserted, causes the processor to complete the

current instruction and issue a stop grant bus cycle. Once the

stop grant is issued, the processor stops the clock, retaining the

ability to execute inquire cycles.

TCK Test Clock Input

TCK is a test clock signal. It conforms to the IEEE-1149.1

boundary scan interface.

TDI Test Data Input Input

The TDI signal is a serial input for test data and TAP instruc-

tions. The instructions or data are sampled on the rising edge

of the TCK signal.

TDO Test Data Output Output

The TDO signal is a serial output for test data and TAP instruc-

tions. TDO is updated on the falling edge of the TCK signal.

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AMD K5 Manual do Utilizador Página 33