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AMD-K5 Processor Data Sheet 18522F/0—Jan1997

PRELIMINARY INFORMATION

BF1–BF0 (Model 1

and Model 2)

Bus Frequency Input

For the AMD-K5 model 1 and model 2 processors, the BF1 and

BF0 signals determine the internal operating speed of the pro-

cessor. The frequency of the CLK signal is multiplied inter-

nally by a ratio determined by the states of the BF1 and BF0

signals during RESET. The processor speed multiplier is deter-

mined as shown below:

BOFF Backoff Input

The processor will transition to a bus hold state and float the

associated signals on the clock that BOFF is sampled as

asserted. An alternate master may drive the bus signals on the

clock after BOFF is sampled asserted. When BOFF is negated,

the processor will restart any bus cycle from the beginning.

Burst cycles interrupted by BOFF will restart from the begin-

ning of the burst cycle. BOFF takes priority over BRDY. If

BRDY is sampled asserted in the same cycle as BOFF, the cycle

will be restarted. (See Switching Characteristics t

and t

BRDY Burst Ready Input

BRDY is sampled on the second and following clocks of a bus

cycle to indicate completion of a data transfer cycle. BRDY is

ignored at the end of the first clock of a bus cycle and when the

bus is in an idle state. The data bus is sampled when BRDY is

asserted. Up to four assertions of BRDY are needed to com-

plete the bus cycle. (See Switching Characteristics t

and t

BRDYC Burst Ready Copy Input

BRDYC is functionally identical to BRDY. These signals are

connected internally by an OR gate. BRDYC is typically used

by level two cache. At the falling edge of RESET, the states of

BRDYC and BUSCHK control the drive strength on the A21–

A3 (not including A31–A22), ADS, HITM, and W/R signals. The

drive strength is weak for all states of BRDYC and BUSCHK

except when BRDYC and BUSCHK are both Low, in which case

BF1 Pin BF0 Pin Internal Clock Multiplier

0 0 1.75

0 1 Reserved

1 0 1.5

1 1 1.5

1 2 ... 21 22 23 24 25 26 27 28 29 30 31 ... 99 100

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