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18522F/0—Jan1997 AMD-K5 Processor Data Sheet

PRELIMINARY INFORMATION

AP Address Parity Input/Output

The AP signal provides even parity for the address bus. This

signal is driven simultaneously with the address bus. Inquire

cycles that do not provide even parity in the same clock cycle

as EADS will result in the assertion of APCHK. (See APCHK.)

APCHK Address Parity Check Output

If the processor detects an address parity error on the address

bus for inquire cycles, APCHK is asserted on the second clock

after EADS is sampled . It remains active for one clock.

BE7–BE0 Byte Enables Output

The BE7–BE0 signals indicate active bytes during read and

write cycles. The eight byte-enable signals correspond to the

eight bytes of the data bus as follows:

These signals are driven at the same time as the address bus.

The byte-enable signals are also used to decode special cycles

as defined in Table 6.

BF (Model 0) Bus Frequency Input

For the AMD-K5 Model 0 processor, the BF signal determines

the internal operating speed of the processor. The frequency of

the CLK signal is multiplied internally by a ratio determined

by the state of the BF signal during RESET. If BF is sampled

High at RESET, the clock frequency is 1.5x the bus frequency.

If BF is sampled Low at RESET, the clock frequency is 2x the

bus frequency.

■ BE7: D63–D56 ■ BE3: D31–D24

■ BE6: D55–D48 ■ BE2: D23–D16

■ BE5: D47–D40 ■ BE1: D15–D8

■ BE4: D39–D32 ■ BE0: D7–D0

BF Pin Internal Clock Multiplier

0 2

1 1.5

1 2 ... 20 21 22 23 24 25 26 27 28 29 30 ... 99 100

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