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AMD-K5 Processor Data Sheet 18522F/0—Jan1997

PRELIMINARY INFORMATION

7 Signal Descriptions

A31–A5/A4–A3 Address Lines Input/Output

A31–A3 are used with BE7–BE0 to form the address bus. These

signals are outputs to address memory space, I/O space, and

system management memory. A31–A5 are used as inputs for

inquire cycles. A4–A3 are not used during the inquire cycle,

but must be driven to valid levels. During bus hold, address

hold, or back-off, A31–A3 are floated. (See Switching Charac-

teristics t

and t

A20M Address Bit 20 Mask Input

Asserting A20M will mask address bit 20 internally for internal

cache accesses or driving memory cycles on the external bus.

A20M should be asserted only in Real mode. Its effect is not

defined in Protected mode. The state of A20M is ignored dur-

ing transfers to and from SMM memory. A20M is sampled on

every rising clock edge. (See Switching Characteristics t

and

ADS Address Status Output

ADS indicates the beginning of a new bus cycle. Valid

addresses and cycle information are available on the address

bus simultaneously with the assertion of ADS. ADS is floated

during bus hold or back-off.

ADSC Address Status Copy Output

ADSC performs the same function as ADS. It permits greater

fanout. ADSC is normally used to directly drive the cache to

achieve greater speed.

AHOLD Address Hold Input

A31–A3 and AP are floated on the clock after AHOLD is recog-

nized as asserted. Other signals remain active. This allows

another bus master to access the processor’s address bus for a

cache inquire cycle. AHOLD has a small internal pulldown

resistor. (See Switching Characteristics t

and t

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