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AMD-K5 Processor Data Sheet 18522F/0—Jan1997

PRELIMINARY INFORMATION

TMS Test Mode Select Input

The TMS signal is used to select the TAP Test modes. This sig-

nal is sampled on the rising edge of the TCK. TMS has an inter-

nal pull-up resistor.

TRST Test Reset Input

Asserting TRST initializes the TAP controller.

W/R Write/Read Output

The W/R signal is used with other control signals to distinguish

bus cycles and special cycles. These cycles are defined in Table

5 and Table 6 on page 27. W/R is driven active with ADS, and

floated with BOFF and bus hold.

WB/WT Writeback/Writethrough Input

The state of WB/WT determines the MESI cache protocol state

of a data line during cache line fills. When the signal is driven

High, the cache line will be loaded in the exclusive state. When

the signal is driven Low, the cache line will be loaded in the

shared state.

Table 1. Input Pins

Name Type Note Name Type Note

A20M

Asynchronous Note 1 IGNNE Asynchronous

AHOLD Synchronous INIT Asynchronous

BF Synchronous Note 2 INTR Asynchronous

BOFF

Synchronous INV Synchronous Note 5

BRDY

Synchronous KEN Synchronous Note 6

BRDYC

Synchronous NA Synchronous

BUSCHK

Synchronous Note 3 NMI Asynchronous

Notes:

1. A20M may change during RESET or during a serializing event like an I/O write. A state change at other times will result in incorrect

address generation on subsequent memory cycles.

2. BF and FRCMC

are normally connected to V

or V

by a jumper. For correct operation, any change on these signals should be

followed by a RESET.

3. BUSCHK

is sampled in every clock. Any asserted sample is remembered and takes effect on the same clock as the last BRDY.

4. These are sampled in the same clock as BRDY.

5. This is sampled in the same clock as EADS.

6. These are sampled with the first BRDY

or NA and must meet setup to every clock

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